1. Field of the Invention
The present invention relates to a flash memory device having mask ROM cells for sel-test and a test method therefor.
2. Description of the Related Art
In a semiconductor memory, if address signal lines are shorted to each other or disconnected, a plurality of word lines would be simultaneously selected or a wrong word line would be selected. Hence, a test for eliminating a semiconductor memory that has such a defect is performed on semiconductor memories before shipment. In the test, test data is written in a memory and then read out from the memory, and read-out data is compared with the test data.
The flash memory device needs to be erased before a write operation. If a flash memory device is over-erased, a floating gate of a memory cell is positively charged and erroneous read may occur. Therefore, for every memory cell, it is repeated that an erase pulse with a short width is provided to the memory cell, data is read from the same, and it is judged whether or not the erase operation is correctly performed. For this reason, it takes, for example, 5 sec in erase operation of flash memory device, which has caused test time for mass-produced flash memory device to be long.
Accordingly, it is an object of the present invention to provide a flash memory device, having mask ROM cells for self-test, that enables reduction in test time required prior to shipment.
In the 1st aspect of the present invention, there is provided a flash memory device comprising: a memory cell array having a plurality of memory cell blocks, each memory cell block having cells arranged in rows and columns, each row including a word line coupled to a plurality of EPROM cells, each column including a bit line coupled to a plurality of EPROM cells, one of the memory cell blocks being selected by block selection signals, contents of EEPROM cells coupled to a selected word line being read on respective bit lines; a mask ROM cell array having a plurality of mask ROM cell rows and a plurality of mask ROM cell columns, each mask ROM cell row arranged in each memory cell block, different mask ROM cell rows having different contents to each other, each mask ROM cell column having transfer gates coupled to a bit line, each mask ROM cell row including a word line coupled to the transfer gates; a mask ROM cell row selecting circuit, arranged for each mask ROM cell row, for making the transfer gates, which are in the memory cell block corresponding to an activated one of the block selection signals, on-state when a test mode signal is active; and a word decoder, arranged for each memory cell block, for activating one of the word lines in response to input signals of predecoded address when the test mode signal is inactive and corresponding block selection signal is active and for inactivating all the word lines when the test mode signal is active.
With the present invention, the test mode signal is activated, selected one of the block selection signals is sequentially activated to read out contents in the mask ROM cell rows and the read-out data are compared with respective expected values. By the comparison, tests are performed on defects such as short between address signal lines and therefore, erase/write operations that have been effected on EPROM cells are unnecessary, which reduces in test time prior to shipment for mass-produced flash memories.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.